Room IT-Lab : 204
Office Phone 6774
Areas Of Interest Statistical Timing Analysis, Digital circuit design, CAD for VLSI

Statistical timing analysis, Timing analysis and reliability, Bayesian inference techniques in EDA

1. Chithira P. R and V. Vasudevan, A Hierarchical Technique for Statistical Path Selection and Criticality Computation, ACM Transactions on Design Automation of Electronic Systems (TODAES), Vol. 23, No. 1, Article 9, August 2017, pp 1-24 2. Chithira P. R. and V. Vasudevan, Potential Critical Path Selection Based on a Time-Varying Statistical Timing Analysis Framework, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 27, NO. 6, JUNE 2019, pp 1438 - 1449

B.Tech (Electronics and Communication) from Model Engineering College, Cochin

M.Tech (Microelectronics and VLSI design) from NIT Calicut

Ph.D. (Electrical engineering) from IIT Madras