Ph.D (NIT Calicut)
M.Tech in VLSI Design
B.E in Electronics and Communication

1. Anuja George, Jayakumar EP, "Design and Implementation of Hardware-Efficient Architecture for Saturation-based Image Dehazing Algorithm", in Journal of Real-Time Image Processing, 20, 102 (2023), https://doi.org/10.1007/s11554-023-01356-x.
2. Anuja George, Jayakumar EP "Hardware-Efficient DWT Architecture for Image Processing in Visual Sensors Networks", in IEEE Sensors Journal. vol. 23, no. 5, pp. 5382-5390, 1 March, 2023, doi:10.1109/JSEN.2023.3235371.
3. Midde, V.S., Jayakumar, E.P. "Low-cost low-power approximated VLSI architecture for high-quality image scaling in mobile devices", in Journal of Real-Time Image Processing, 20, 11 (2023). https://doi.org/10.1007/s11554-023-01282-y
4. Siva MV, Jayakumar E P “An Inaccurate Median Filter Architecture for Salt and Pepper Noise Removal”, In 3^rd IEEE International Conference on VLSI Systems, Architecture, Technology and Applications (VLSI SATA-2022), (pp.  1-5), 2022.
5. Das LB, Jayakumar EP, Jagadanand G, Meghana O, Satheesh P, Sriharsha R, Prasanna VL, Aswini V. “Design of a Personal Digital Assistant for the Visually Challenged”, In 2022 IEEE International Conference on Industry 4.0, Artificial Intelligence, and Communications Technology (IAICT) 2022 Jul 28 (pp. 15-21).
6. Kartheek P, Jayakumar EP. “Hardware Architecture for Adaptive Edge-Directed Interpolation Algorithm”, In 2022 IEEE International Conference on Industry 4.0, Artificial Intelligence, and Communications Technology (IAICT) 2022 Jul 28 (pp. 1-7).
7. Narendiran S, Jayakumar E P., “An Efficient Modified Distributed Arithmetic Architecture Suitable for FIR Filter”, In 2021 IEEE Sixth International Conference on Wireless Communications, Signal Processing and Networking (WiSPNET) 2021 Mar 25 (pp. 89-93).
8. Siva MV, Jayakumar E P, “Approximated algorithm and low cost VLSI architecture for edge enhanced image scaling”, In 2020 IEEE International Conference on Industry 4.0, Artificial Intelligence, and Communications Technology (IAICT) 2020 Jul 7 (pp. 125-130).
9. Siva MV, Jayakumar EP, ‘A Low Cost High Performance VLSI Architecture for Image Scaling in Multimedia Applications”, In 2020 7th International Conference on Signal Processing and Integrated Networks (SPIN) 2020 Feb 27 (pp. 278-283).
10. Jayakumar, E. P. and P. S. Sathidevi, ”An Integrated Acoustic Echo and Noise Cancellation System using Cross-band Adaptive Filters and Wavelet Thresholding of Multitaper Spectrum”, International Journal of Applied Acoustics (Elsevier), vol.141, pp. 9-18, 2018.
11. P. V. Muhammed Shifas, Jayakumar E. P. and P.S. Sathidevi, ”Robust Acoustic Echo Suppression in Modulation Domain,” in Progress in Intelligent Computing Techniques: Theory, Practice, and Applications, Singapore, Springer Nature Singapore Pte Ltd., 2018, pp. 527-537.
12. Jayakumar E. P., P. V. Muhammed Shifas, and P. S. Sathidevi, ”Integrated acoustic echo and noise suppression inmodulation domain,” International Journal of Speech Technology (Springer), vol.19, no.3, pp. 611-621, 2016.
13. Jayakumar E. P. and P. S. Sathidevi, ”Speech Enhancement Based on Noise Type and Wavelet Thresholding the Multitaper Spectrum,” in Advances in Machine Learning and Signal Processing, Lecture Notes in Electrical Engineering series, Switzerland, Springer International Publishing, 2016, pp. 187-200.
14. Ramanathan SG, Kumar BP, Ananda CM, Jayakumar EP, “Design of graphics processing framework on FPGA,” in IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT-2016), 20-21 May 2016 at Sri Venkateshwara College of Engineering, Bengaluru, India, (pp. 387-391).
15. Dinesh MV, Ananda CM, Kumar BP, Jayakumar EP, “Design and implementation of fiber channel based high speed receiver protocol for avionics on FPGA,” in IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT-2016), 20-21 May 2016 at Sri Venkateshwara College of Engineering, Bengaluru, India, (pp. 1195-1200).
16. Narapureddy P, Ananda CM, Kumar BP, Jayakumar EP, “Design and implementation of fiber channel based high speed serial transmitter for data protocol on FPGA,” in IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT-2016), 20-21 May 2016 at Sri Venkateshwara College of Engineering, Bengaluru, India, (pp. 926-931).

1. Digital System Design

2. DSP System Design

3. VLSI System Design

Ongoing

ARATHI SANKAR P (Full Time)

ANUJA GEORGE (Full Time - QIP)

MIDDE VENKATA SIVA (Full Time)

ANJU GEORGE (Part-time)