Ph.D.  :IIT Delhi, 2017

M.Tech.: NIT Calicut,Digital Systems & Communication, 2007

B.Tech.: NIT Calicut, Electronics & Communication Engineering,2003

PhD Completed:

1. Ms. Remya Jayachandran
Topic of Research: High performance OTA  buffer designs for resistive loads

2.Ms. Sona Alex 
Topic of research: Design and Development Of Secure And Energy-Efficient Schemes 
for Health Data Processing In Mobile Healthcare Networks
(Combined Guidance with Dr. Deepthi P. P.)

 
3. Mr. Nithin Thomas Abraham 

Topic of research: Modeling and Low-Power Analog Circuit Based Control Strategies 
of Single Inductor Multiple- Output (SIMO) DC-DC Converters for Portable Electronic Devices

Research Scholars:

1. Mr. Sasi Kiran Suddarsi

Topic of Research: Low power device(s) modelling and low power digital circuit design
(Combined Guidance with Dr. Gopi Krishna Saramekala)

2. Ms. Maleeha Abdul Azeez
Topic of Research: Low Power Analog IC design 

3. Ms. Bini V.K.
Topic of Research: Neuromorphic Computing Hardware 

4. Ms. Anju C.
Topic of Research: Neural Network Accelerators 

Journal:

1. S.K. Suddarsi, G.K. Saramekala, Dhanaraj K .J., " Investigation of Switching and Inverter Characteristics of Recessed-Source/Drain (Re-S/D) Silicon-on-Insulator (SOI) Feedback Field Effect Transistor (FBFET)”, Microelectronics Journal (Elsevier) (Accepted for publication)  
2. Alex, S., Dhanaraj, K.J. and Deepthi, P.P., 2022.  "Energy Efficient and Secure Neural Network-based Disease Detection Framework for Mobile Healthcare Network". ACM Transactions on Provacy and Security, 2023 Apr 15;26(3):1-27.
3. N.T. Abraham, G. Chowdary, Dhanaraj K. J, A State Separate Modular Modeling Methodology of Multi-Output DC-DC Converters. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 2022 Jun 27;42(3):968-77
4. Remya J, Subramaniam PC, Dhanaraj KJ.  "Planar CMOS And Multigate Transistors Based Wide-Band Ota Buffer Amplifiers For Heavy Resistance Load", Facta Universitatis, Series: Electronics and Energetics 2022 Mar 25;35(1):013-28
5. Alex, S., Dhanaraj, K.J. and Deepthi, P.P., 2022. "Private and Energy-Efficient Decision Tree-Based Disease Detection for Resource-Constrained Medical Users in Mobile Healthcare Network". IEEE Access, 2022 Feb 7;10:17098-112.
6. Remya J, Subramaniam PC, Dhanaraj KJ. "A novel tunable gain CMOS buffer amplifier for large resistive loads". Integration The VLSI Journal, Vol. 77, March 2021, Pages 1-12  https://doi.org/10.1016/j.vlsi.2020.10.007
7. Sona Alex, Deepthi P P, Dhanaraj K. J., " SPCOR: A Secure and Privacy-Preserving Protocol for Mobile-Healthcare Emergency to Reap Computing Opportunities at Remote and Nearby", IET Information Security,2020 Jun 10;14(6):670-82
8. Prasannakumar, A., Abraham, N.T. & Dhanaraj, K. "MOSFETs-only sub-1-V voltage references for ultra-low-power applications". Analog Integr Circ Sig Process 103, 355–365 (2020). https://doi.org/10.1007/s10470-020-01619-8
   
9. Celine Mary Stuart, Spandana K., Dhanaraj K.J., Deepthi P. P., "Design and Implementation of Hardware-Efficient Modified Rao-Nam Scheme with High Security for Wireless Sensor Networks", Journal of Information Security and Applications, vol 29, pp 65-79, 2016 (doi:10.1016/j.jisa.2016.03.004)
10. Dhanaraj. K.J, Deepthi.P.P and P.S. Sathidevi, "FPGA Implementation of a Pseudo Random Bit Sequence Generator Based on Elliptic Curves", ICGST- PDCS Journal, Volume 7, Issue 1, pp. 23-31, May 2007

Conference:

1. Shalu Francis, Anjana Ouseph, Durgaprasad S., Hani Abdulla, Akhil Lal, S. Likhith, Dhanaraj K. J., Harikrishna M. " Machine Learning based Vacant Space Detection for Smart Parking Solutions", IEEE International Conference on Control, Communication and Computing (ICCC 2023), Thiruvananthapuram, India, May 19-21, 2023
2. Appukuttan A, Thomas E, Nair HR, Hemanth S, Dhanaraj KJ, Azeez MA. "In-Memory Computing Based Hardware Accelerator Module for Deep Neural Networks".  IEEE 19th India Council International Conference (INDICON) 2022, Kochi, India, Nov 24 (pp. 1-6) 
3. Alex, S., Dhanaraj, K.J. and Deepthi, P.P.,"Secure Integer Comparison Protocol For ML-based Disease Diagnosis In MHN With Energy Efficient Edge Computing", 2022 56th Annual Conference on Information Sciences and Systems (CISS), Princeton University, Mar 9-11, 2022
4. K.M.Sankar Nampoothiri, Kalyani N Menon, Sayed Muhsin, Senna Manoj, Sooraj P, Dhanaraj K J, Deepthi P P, " A High Throughput QC-LDPC Decoder Architecture for Near Earth SatelliteCommunication", 2021 4th International Conference on Circuits, Systems and Simulation (ICCSS 2021),Kuala Lumpur, Malaysia,May 26-28, 2021 
5. Remya Jayachandran, K J Dhanaraj, P C Subramaniam, "Hardware realization and testing of multistage OTA buffer amplifier for heavy resistive load", 4th international conference on  Devices for Integrated Circuit (DevIC 2021), Kalyani, West Bengal, India, May 19-20, 2021 
6. U. Venkatesh, M. P. Kumar, R. Saketh, C. U. R. Sai, S. V. K. Naik and K. J. Dhanaraj, "An Analog Design of 2D DCT Processor," TENCON 2019 - 2019 IEEE Region 10 Conference (TENCON), Kochi, India, 2019, pp. 1606-1610.
7. Sabir K. A. Ahammed ; Charls Babu ; V. R. Ranjith ; M. Unnikrishnan ; Supriya Unnikrishnan ; K. J. Dhanaraj, G. Sreelekha, "FFT Architecture for Motion Estimation using Phase Correlation," TENCON 2019 - 2019 IEEE Region 10 Conference (TENCON), Kochi, India, 2019, pp. 316-320.
8. A. T. Pullan, A. Sasi, D. Krishnan, I. M. Baby, M. Krishnan and D. K. J, "High Resolution Touch Screen Module," 2018 IEEE Recent Advances in Intelligent Computational Systems (RAICS), Thiruvananthapuram, India, 2018, pp. 168-171.
9. Jinesh K.B, and K.J. Dhanaraj, " A Low Power Architectute of Real Time Stereo Vision Algorithm Using Discrete Cosine Transform", TENCON 2017 IEEE Region 10 Conference, Penang, Malaysia, 5-8 Nov, 2017
10. Dhanaraj K.J and Basabi Bahumik, “ Modulation Ratio of Layer 2/3 cells in Primary Visual Cortex: A Model Based Study”, 2015 International Joint Conference on Neural Networks (IJCNN), Killarney, Ireland, July 12-17, 2015
11. Aravind E. Vijayan, Asma Beevi K.T., Kevin Jerome, Karthika C. Ravaindran, Dhanaraj K.J., " High SNR EMG Acquisition System for Biofeedback applications",IEEE - International Conference on Computational Intelligence & Communication Technology, Gaziabad, India, Feb. 13-14, 2015
12. Prakash, Gundabathina, and K. J. Dhanaraj, "A g_m/I_D based Design of High PSR Low dropout Regulator for SoC Applications", 2015 International Conference on Communication, Information & Computing Technology (ICCICT),, Mumbai, India,  Jan. 16-17, 2015
13. Jerome, Kevin, Varghese Tony, R. Vinayak, and K. J. Dhanaraj. "Indoor Navigation Using Visible Light Communication." 2014 IEEE Texas Instruments  India Educators' Conference (TIIEC), pp. 46-52,2014.
14. Nithin V.S., Deepthi P.P., Dhanaraj K.J., Sathidevi P.S., "Stream Ciphers Based on Elliptic Curves", International Conference on Computational Intelligence and Multimedia Applications (ICCIMA 2007), Sivakasi, Tamilnadu, December 13-15, 2007

1. Title : Special Manpower Development Programme - Chip to System Design (SMDP-C2SD) 

Role : Principal Investigator (Co-PI: Mr. Bhuvan B.)

Funding Agency: DeitY

Duration 2015-2020  (Completed)

2. Title: VLSI implementation of LDPC Encoder/Decoder for  On-board/Ground Satellite Applications

Role : Co-Investigator (PI: Dr. Deepthi P. P.)

Funding Agency: ISRO (RESPOND Scheme)

Duration: 2019-21 (Completed)

3. Title: Image based Smart Parking Management for Intelligent Transportation Systems

Role : Co-Investigator (PI: Dr. Harikrishna M, Asst. Prof, CED)

Funding Agency: KSCSTE

Duration: 2020-22 (Completed)

4. Title: DST –FIST funded Project (Level – I category) for augmenting the research facilities in Wireless Communication and Signal Processing areas 

Role : Co-Investigator (PI: Dr. Sameer S. M.)

Funding Agency: DST

Duration: 2018-23 

5. Title: High-Fidelity Sinusoidal Synthesizer for HRG Whole Angle Tracking

Role : Principal Investigator (Co-PI: Dr. Deepthi P. P.)

Funding Agency: ISRO (RESPOND Scheme)

 Duration: 2023-25 

6. Title: High Precision Interfacing Circuits for Capaitive based Sensors for Defence Applications

Role : Principal Investigator (Co-PIs: Dr. Bhuvan B, Dr. Ashutosh Mishra)

 Funding Agency: MeitY (SMDP-C2S) 

 Duration: 2022-2027 

M.Tech Major Projects:
 
 1.  SRAM Design and Standby Power Minimization (2007-08)
 2. Design of Low Power Wideband Analog Multiplier(2008-09)
 3. Design and Simulation of High Gain-Bandwidth Fully Differential Operational Amplifier(2008-09)
 4. EMG Acquisition System for Control Applications(Wheel Chair Control)
   ( Combined Guidance With Mr. Raghu C.V., Assistant Professor, ECED) (2009-10)
 5. Low Power Ternary CAM Design and Simulation (2009-10)
 6. A gm/ID based High PSR Low Dropout Regulator Design (2013-14)
 7. Hardware Design For Secret Key Cryptosystem Using Regular Quasi-Cyclic LDPC 
     Codes (2014-15)
 8. ASIC Implementation of Real Time Stereo Vision Algorithm Using Discrete Cosine Transform (2014-15)
9. ASIC  Implementation of Low Power-High Speed Fixed/Floating point MAC Unit (2015-16)
10. Hardware Implementation of Code based Cryptographic system using QC-LDPC (Combined Guidance with Dr. Deepthi P. P.)(2016-18)
11. Design of Low Power Event Driven Clockless Level Crossing ADC  (combined Guidance with Mr. Bhuvan B.)(2016-17)
12. Hardware Implementation of Code Based Cryptographic system Using QC-LDPC Codes (2016-18)
13. ASIC Implementation of Regular LDPC-CC Encoder and Decoder (2017-18)
14. Efficient Hardware Implementation of Encoder and Decoder for Polar Codes (combined Guidance with Dr. Deepthi P. P.) (2018-19)
15. Ultra Low Power MOSFET-Only Voltage References (2018-19)
16. Hardware Implementation of LDPC Encoder and Decoder for Space Applications (2019-20)
17.Image Processing Based Smart Parking System (2021-22)
18. High Resolution Sinusoidal Frequency Snthesizer for HRG Whole Angle Tracking (Ongoing)

 B.Tech Major Projects: 

1. Implementation Of A Video Conferencing Application Over A Wired Network ( Combined 
 Guidance With Dr. P.S. Sathidevi, Asst.Professor,ECED) (2005-06)
2. Desgin and Simulation of a High Slew Rate Operational Amplifier (2007-08)
3. FPGA Implementaion of AES Cryptosystem (2007-08)
4. Selective Image Encryption( Combined Guidance With Ms. Deepthi P.P., Lecturer, ECED) (2008-09) 
5. Implementation of Reed Solomon Encoder and Decoder (2008-09) 
6. FPGA Implementation of Network Intrution Detection System(2008-09) 
7. Wearable Emergency Alert System (2009-10)  
8. SONAR Aided Object Localization (Combined Guidance with Dr. Sameer S.M.) (2014-15) 
9. BIO Monitoring System using FPGA board (2016-17) 
10. Monocular Visual Simultaneous Localization and Mapping (combined guidance with Dr. Sudheer A. P, MED) (2016-17)
11. Low Cost Touch Sensitive Screen Module (2016-17)
12. Implementation of 2D DCT in Digital and Analog Domains (2017-18)
13. FFT Architectures for Motion Estimation Using Phase Correlation (Combimed Guidance with Dr. Sreelekha G.)(2017-18)
14. SAD Based Real Time Stereo Vision Algorithms: A Comparative Study and Protoype Implementation (2017-18)
15. Hardware Implementation of LeNet-5 Architecture for Convolutional Neural Networks (2018-19)
16. Hardware Implementation of LDPC Encoder and Decoder for Space Applications  (2018-19)
17. Image Based Smart Parking Management for Intelligent Transportation Systems (Combimed Guidance with Dr. Hariksishna M., CED)(2020-21)
18.VLSI Implementation of a High Throughput QC-LDPC Encoder and Decoder for Satellite Applications
19. Hardware accelerator Modules for Deep Neural Networks (2021-22)
20. Low power All CMOS Voltage Reference (Ongoing)
21. Process variation study of Analog CMOS spiking neuron Circuits (Ongoing)

1. EC4068D Analog MOC Integrated Circuits (H Slot)

2. EC6202E Analog Integrated Circuit Deisgn (C1, QA1 Slots)

Membership:

1. Member - IEEE

2. Member - IEEE Solid-State Circuits Society

3. Member - IEEE Circuits and Systems Society

Official Positions:

1. Vice Chair, Circuits and Systems Society, IEEE Kerala chapter (2020,2021)

2. Secretary, Educational  Activities, IEEE Kerala chapter (2019)

3. Secretary, Circuits and Systems Society, IEEE Kerala chapter (2017,2018)

4. Treasurer, IEEE Malabar Sub-Section (2017, 2018)

5. SB Counselor, IEEE Student Branch, NIT Calicut (2015, 2016)

1. Digital Integrated Circuit Design

2. Electronic Circuits I (UG)