Room ECED-2 : 208
Email suryaprakash@nitc.ac.in
Office Phone 04952286734
Areas Of Interest Signal Processing algorithms and VLSI Architectures, VLSI for communications, VLSI for multimedia, ASIC design.
  1. B.Tech, JNTU Kakinada, 2009.
  2. Ph.D, IIT Guwahati, 2016.

 

S. No.

Position

Department

University/Institute

Type of Institute

Duration

Year

1.

Research Scholar

Electronics and Electrical Engineering

IIT Guwahati

Central Government

7 years

2009-2016

2.

Ad-hoc Faculty

Electronics and Communication Engineering

NIT-Andhra Pradesh

Central Government

9 months, 20 days

July-24th, 2017 to May 14th, 2017

3.

Assistant Professor

Electronics and Communication Engineering

NIT-Calicut

Central Government

 

June-2018 to today

 

 

Semester

Course

Year of Study and Branch

Monsoon-2018

ZZ1003D Basic Electrical Sciences

B. Tech Ist year (CSE, CE)

EC3091 Electronic Circuits-II Laboratory

B. Tech IIIrd year (ECE)

Winter-2018

EC2091D Electronic Circuits-I

B. Tech IInd year (ECE)

EC2093D Electronic Circuits-I laboratory

B. Tech IInd year (ECE)

Monsoon-2019

ZZ1003D Basic Electrical Sciences

B. Tech Ist year (ME, PE)

EC6402D Digital Signal Processing Algorithms

M. Tech Ist year (ECE) (SP)

EC2091D Devices and Networks Laboratory

B. Tech IInd year (ECE)

Winter-2019

ZZ1003D Basic Electrical Sciences 

B. Tech Ist year (ECE, EEE)

EC2091D Electronic Circuits-I

B. Tech IInd year (ECE)

EC2093D Electronic Circuits-I Laboratory

Monsoon-2020

EC6402D Digital Signal Processing Algorithms

M. Tech Ist year (ECE) (SP)

EC3013D Digital Signal Processing

B. Tech IIIrd year (ECE)

Winter-2020

 

 

EC2091D Electronic Circuits-I

B. Tech IInd year (ECE)

EC2093D Electronic Circuits-I Laboratory

EC3093D Digital Signal Processing Laboratory

B. Tech IIIrd year (ECE)

Monsoon-2021

 

EC2011D Electric Circuits and Network Theory

B. Tech IInd year (ECE)

EC2093D Devices and Networks Laboratory

B. Tech IInd year (ECE)

 

 

 

Year

Title of the Program

2018-19

  1. Faculty Coordinator, ECE-Association (jointly with Dr. Dhanaraj K. J.).

  2. Member of the Exam Vigilance Committee of ECED (jointly with Shri. Suresh, Dr. Venu Anand and Dr. V. Sakthivel and Dr. Venu Anand).

  3. Member of the B. Tech Project Evaluation Committee for Embedded & VLSI specializations (jointly with Dr. Deepthi P. P. and Shri. Bhuvan B.).

  4. Member of the Volunteer Services Committee for 15th Convocation of NIT-Calicut.

  5. Member of M. Tech project Evaluation Team for Internship students.

  6. Member of Stock Verification Team for Annual Stock Verification 2018-19.

  7. Committee Member for Annual Sports Meet-2019 held at NIT-Calicut.

2019-20

  1. Time-table In-Charge for ECED (jointly with Dr. Bindiya T. S.).

  2. Member of the Exam Vigilance Committee of ECED (jointly with Dr. Ali C. K., Dr. Venu Anand and Dr. Sudeep P. V.).

  3. Member of the B. Tech Project Evaluation Committee for Embedded & VLSI specializations (along with Shri. Raghu C. V. and Shri. Bhuvan B.).

  4. Faculty Advisor for the 2019-23 batch of ECE students (jointly with Dr. Praveen Sankaran, Dr. Suja K. J. and Dr. Gopi Krishna S.).

  5. Member of the Announcements Committee for Annual Sports Day.

  6. Mentor Faculty from ECED for students internship under TEQIP Twinning program (jointly with Dr. Venu Anand).

  7. Application Scrutinization Committee member for Ad-hoc Faculty Interviews held during Monsoon-2019.

2020-21

  1. Time-table In-Charge for ECED (jointly with Dr. Bindiya T. S.).

  2. Faculty Incharge for Electronic Circuits Lab of ECED.

  3. Faculty Advisor for the 2019-23 batch of ECE students (jointly with Dr. Praveen Sankaran, Dr. Suja K. J. and Dr. Gopi Krishna S.).

  4. Committee Member for Disposal/Write-Off of unserviceable items.

  5. Committee Member for preparation of Self-Assessment Report (SAR) for MTech Telecommunications specialization.

  6. Member of the General Arrangements Committee for National Board of Accreditation Work for Telecommunications Specialization.

 

 

S. No.

Title of the Program

Venue

Duration

1.

TEQIP sponsored FDP on “ARM based Embedded System Development”

ECED, NIT-Calicut.

7 days (17/06/2018 - 23/06/2018).

2.

Workshop on Outcome Based Education & Institutional Academic Quality Assurance

ECED, NIT-Calicut

1 day (13/12/2018)

3.

TEQIP sponsored FDP on “Advanced Pedagogy Training Programme”

Teaching Learning Centre, IIT Madras.

3 days (21/03/2019 - 23/03/2019).

4. 

Expert Talk on Signal Processing in FDP on “Research Trends in Multimedia and Multirate Signal Processing” (RTMMSP’19)

ECED, NIT-Calicut, (By Prof. Sivaji Chakravorti)

6 days (24/06/2019 - 29/06/2019)

5. 

TEQIP sponsored Productivity Enhancement Program

NIT-Calicut

4 days (16/07/2019 - 19/07/2019).

6.

Expert Talk on “Control Path Design for Digital SOCs - using Embedded Processors”

ECED, NIT-Calicut, (By Mathews John)

08/08/2019

7. 

TEQIP sponsored course on Digital Transformation in Teaching and Learning Process

IIT Bombay (Online)

2 weeks (06/04/2020 - 22/04/2020).

8. 

Training for Xilinx Artix-7 AC701 Evaluation Kit Usage

NIT-Calicut (Online)

22nd June, 2020

9.

Two Hour Professional Workshop on “Prior-Art Searching with Google Patents”

Turnip Innovations, Mumbai (Online)

05/09/2020

 

 

S. No.

Title of the Program

Venue

Duration

1.

Self Sponsored Five-Day Online Short Term Training Program (STTP) on “VLSI Architectures for Digital Signal Processing Systems”

NIT-Calicut (Online, jointly with Dr. Ashutosh Mishra)

5 days (14th June, 2021 - 18th June, 2021)

S. No.

Title of the Talk/Lecture and Program Details

Venue

Duration

1.

VLSI Digital Signal Processing in FDP on Research Trends in Multimedia and Multirate Signal Processing (RTMMSP’19)

Organized by Dr. Sakthivel, ECED, NIT-Calicut

6 days (24/06/2019 - 29/06/2019)

2. 

Lecture on Introduction to VHDL/Verilog Design for Logic Circuits

Organized by GEC Kozhikode under Visiting Faculty Scheme

1 day - 2 Hours (13th December, 2020 10:00AM)

3.

VLSI Digital Signal Processing Systems in STTP on VLSI Architectures fo Digital Signal Processing Systems (VADSPS-21)

Organized by Self (along with Dr. Ashutosh)

1 day - 1.25 Hours (14th June, 2021, 11:15AM - 12:30PM)

4.

VLSI Digital Signal Processing Systems in STTP on VLSI Architectures fo Digital Signal Processing Systems (VADSPS-21)

Organized by Self (along with Dr. Ashutosh)

1 day - 1.25 Hours (16th June, 2021, 09:30AM - 10:45AM)

5.

VLSI Digital Signal Processing Systems in STTP on VLSI Architectures fo Digital Signal Processing Systems (VADSPS-21)

Organized by Self (along with Dr. Ashutosh)

1 day - 1.25 Hours (18th June, 2021, 11:15AM - 12:30PM)

6.

Lecture on High Throughput Architecture for LMS Adaptive Filter Using Distributed Arithmetic in International Conference on Advances in Signal Processing and Communications (NEC-ICASPC-2K21)

Organized by Narasaraopeta Engineering College, A. P.

1 day - 1 Hour (24th July, 2021, 10:00AM - 11:00AM)

 

S. No.

Title of the Program

Type of Event

Role

Venue

Duration

1.

VLSI Design and Test (VDAT-2020)

Conference

Reviewer

IIT Bhubaneswar

6 days (24/06/2020 - 29/06/2020)

2. 

Seventh IEEE Uttar Pradesh Section International Conference on Electrical, Electronics and Computer Engineering (UPCON 2020)

Conference

Reviewer

MNIT Allahabad

3 days (27/11/2020 - 29/11/2020)

3.

National Conference on Advances in Computing Communications Signals Energy and Technology (ACCSET 2021)

Conference

Reviewer

College of Engineering Vadakara

2 days (26/05/2021 - 27/05/2021)

 

 

S. No.

Title of the Project

Program and Nature of Project

Name and Roll No. of Student

Year

1. 

Wireless Electrocardiogram

B. Tech (Mini project)

Radhika R Kurup (B160089EC), Syeda Mahin (B160820EC), Mishab I  (B160773EC), 

Radhul Dev  M (B160353EC), Mahanti Sandhyana (B160696EC)

2018-19

2.

Fire Detection and Smart Alerting System

B. Tech (Mini project)

Dunna Akhila (B160694EC),   

Kanchustambham Satya Sai Pavan Kumar (B160622EC), 

Ladi Vinod Kumar (B160872EC), 

Karri Anjana Lakshmi (B160659EC)

2018-19

3.

Indoor Positioning System (jointly with Smt. Lyla B. Das)

B. Tech (Major Project)

Abhay Chandran (B150868EC), A. Yashwanth Sai (B150855EC), C. Vamsi Narayana reddy (B150530EC), D. Manoj (B150624EC), K. Rahul Chowdary (B150713EC)

2018-2019

4. 

Hardware Implementation of LeNet-5 Architecture for

Convolutional Neural Networks (jointly with Dr. Dhanaraj K. J.)

B. Tech (Major Project)

Manish Murali C (B150586EC),

N Srinu (B150998EC), 

Punya S M (B150178EC), 

Sandeep J Nair (B150910EC), 

V Praneesha (B150786EC)

2018-2019

5. 

FPGA Implementation of DTMF Signal

Detection and Its Piano Application

B. Tech (Major Project)

Kota Sri Navya (B160454EC), 

Nandipati Anu Deepthika (B160892EC), 

Sri Ramya Movva (B160130EC), 

Dunna Akhila (B160694EC), 

Bhukya Soumya Mishra (B160410EC)

2019-2020

6. 

Hardware Implementation of Distributed Arithmetic Based Adaptive Filter

M. Tech, VLSI (Major Project)

Inturi Goipchand (M180118EC)

2019-2020

7.

PNP Analysis on Next Generation CPU Cores: Maximizing Performance for a given Power Budget

M. Tech, VLSI (Major Project) (Intern at Intel, Bangalore)

Avika Tyagi (M180231EC)

2019-2020

8.

Analysis of Formal Methods to Achieve Bug Free Design

M. Tech, VLSI (Intern at Intel, Bangalore)

M. Vijay (M180448EC)

2019-2020

9. 

Design Verification of different architectural modules/blocks in Nvidia Tegra SoC

M. Tech (EDT) (Internship at Nvidia, Bangalore)

Shouvik Mukhopadhyay (M180374EC)

2019-2020

10. 

A Distributed Arithmetic Based Adaptive Equalizer Implementation on DSP Processor Platform

M. Tech (Telecommunication)

Adarsh D. M. (M180428EC)

2019-20

 

 

S. No.

Name of the Scholar

Title of Thesis

Research Field

Program

Year of Joining

Status

1.

Kopperundevi P.  (B180012EC)

Design of Hardware Architecture for Deblocking Filter in HEVC

VLSI for Multimedia

Regular

2018 (July)

Ongoing

2. 

Vidyamol K. (P200078EC)

VLSI for ML/Communications

VLSI for ML

Part-time

2021 (January)

Ongoing

 

 

S. No.

Grant

Title of the project

Funding Agency/Institute

Duration

Status

1.

Faculty Research Seed Grant-2019 (FRG-2019)

Design and Implementation of Distributed Arithmetic Based Adaptive Equalizers for Wireless Communications

NIT-Calicut

2 years (2019-21)

Ongoing

 

 International Journals:

  1. M. Prakash and R. Shaik, "Low-area and high-throughput architecture for an adaptive filter using distributed arithmetic," IEEE Trans. Circ. Syst. II, Exp. Briefs., vol. 60, no. 11, pp. 781–785, Nov 2013.
  2. M. Prakash, R. Shaik and K. Sagar, "An Efficient Distributed Arithmetic based realization of the Decision Feedback Equalizer," Circ. Sys. and Sig. Process., Springer, vol. 35, issue. 2, pp. 603-618, Feb 2016.
  3. M. S. Prakash, R. Shaik, "DA based approach for the implementation of block adaptive decision feedback equalizer," IET Sig. Process., vol. 10(6), pp. 676-684, Aug 2016.
  4. Mohd Tasleem Khan, Rafi Ahamed Shaik, Surya Prakash M, "Improved convergent distributed arithmetic based low complexity pipelined least-mean-square filter," IET Circ., Dev., Sys., Apr 2018.
  5. M. Surya Prakash, Rafi Ahamed Shaik, "A Distributed Arithmetic Based Realization of Least Mean Square Adaptive Decision Feedback Equalizer Using Offset Binary Coding Scheme", Elsevier Signal Processing, 2021.
  6. P. Kopperundevi, M. Surya Prakash, Rafi Ahamed Shaik, "A High Throughput Hardware Architecture for Deblocking Filter in HEVC" accepted for publication in Elsevier Signal Processing: Image Communication.

 National and International Conference Proceedings:

  1. M. Surya Prakash and R. Shaik, "High performance architecture for LMS based adaptive filter using distributed arithmetic," in Int. Conf. Inform. and Comput. Applicat. (ICICA), vol. 24, pp. 18-22, Mar. 2012.
  2. M. Prakash and R. Shaik, "Low complexity hardware architectural design for adaptive decision feedback equalizer using distributed arithmetic," in IEEE Int. Conf. Comput. Syst. and Ind. Informatics (ICCSII), pp. 1-5, Dec. 2012.
  3. M. Surya Prakash and R. Shaik, "A Distributed Arithmetic based Approach for the Implementation of the Sign-LMS Adaptive Filter," in IEEE Int. Conf. on Sig. Process. and Commun. Eng. Syst. (SPACES), pp. 326-330, Jan. 2015.
  4. P. Kopperundevi, M. Surya Prakash, "A Hardware Architecture for Sample Adaptive Offset Filter in HEVC", accepted for publication in IEEE DISCOVER-2021.

Book Chapters:

  1. Kopperundevi, P., and Surya Prakash, M., (2021) “An Efficient Hardware Architecture For Deblocking Filter in HEVC”, in chapter in Innovations in Springer Electrical and Electronic Engineering, vol. 661, Jan-2021.

 

 

Year

Title of the Program

2015 - today

Working as Reviewer for Springer Circuits, Systems and Signal Processing Journal.

2015-16

Worked as Reviewer for Twenty Second National Conference on Communications (NCC-2016) held at IIT Guwahati from 04/03/2016 to 06/03/2016.

2017-18

Worked as Reviewer for Twenty Fourth National Conference on Communications (NCC-2018) held at IIT Hyderabad from 25/02/2018 to 28/02/2018.

2018-19

  1. Participated in All India Inter NIT Tournament (Faculty & Staff) held in December-2018 at NIT-Goa.

  2. Accompanied 2016-20 batch of students for Industrial Visit (National Institute of Oceanography).

2019-20

  1. Worked as Micro-observer for counting duty of Indian Loksabha Elections - 2019.

  2. Participated in TEQIP-III sponsored One Day Workshop on Basic Life Support - First Responder Training held at NIT-Calicut.

  3. Participated in All India Inter NIT Faculty and Staff Cricket Tournament held in December-2019 at VNIT-Nagpur.

 

 

S. No.

Degree

University/Institute

Year

1.

Vice Election Officer for Students Gymkhana Elections 2012-13

IIT Guwahati

2012-13

2.

Warden for Boys Hostel

NIT-Andhra Pradesh

2017-18

3.

Faculty Incharge for Institute Internet Connectivity 

NIT-Andhra Pradesh

2017-18

4.

Faculty Advisor in the department of ECE

NIT-Andhra Pradesh

2017-18

5.

Head of the Disciplinary Committee of the Institute

NIT-Andhra Pradesh

2017-18

 

Memberships:

1. Member, IEEE.

Biology, Consciousness Studies, Spiritual Science.

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