Room ECED-1 : DB101
Email jay@nitc.ac.in
Office Phone 0495-2286732
Mobile 9497467811
Home Address Eruppathodiyil House, Opp RECGVHSS, NIT Campus PO, Calicut - 673601
Areas Of Interest Speech and Audio Processing, VLSI Architecture for Digital Signal Processing, Digital IC design

Ph.D (NIT Calicut)
M.Tech in VLSI Design
B.E in Electronics and Communication

  1. Narendiran S, Jayakumar E P., “An Efficient Modified Distributed Arithmetic Architecture Suitable for FIR Filter”, In 2021 IEEE Sixth International Conference on Wireless Communications, Signal Processing and Networking (WiSPNET) 2021 Mar 25 (pp. 89-93).
  2. Siva MV, Jayakumar E P, “Approximated algorithm and low cost VLSI architecture for edge enhanced image scaling”, In 2020 IEEE International Conference on Industry 4.0, Artificial Intelligence, and Communications Technology (IAICT) 2020 Jul 7 (pp. 125-130).
  3. Siva MV, Jayakumar EP, ‘A Low Cost High Performance VLSI Architecture for Image Scaling in Multimedia Applications”, In 2020 7th International Conference on Signal Processing and Integrated Networks (SPIN) 2020 Feb 27 (pp. 278-283).
  4. Jayakumar, E. P. and P. S. Sathidevi, ”An Integrated Acoustic Echo and Noise Cancellation System using Cross-band Adaptive Filters and Wavelet Thresholding of Multitaper Spectrum”, International Journal of Applied Acoustics (Elsevier), vol.141, pp. 9-18, 2018.
  5. P. V. Muhammed Shifas, Jayakumar E. P. and P.S. Sathidevi, ”Robust Acoustic Echo Suppression in Modulation Domain,” in Progress in Intelligent Computing Techniques: Theory, Practice, and Applications, Singapore, Springer Nature Singapore Pte Ltd., 2018, pp. 527-537.
  6. Jayakumar E. P., P. V. Muhammed Shifas, and P. S. Sathidevi, ”Integrated acoustic echo and noise suppression inmodulation domain,” International Journal of Speech Technology (Springer), vol.19, no.3, pp. 611-621, 2016.
  7. Jayakumar E. P. and P. S. Sathidevi, ”Speech Enhancement Based on Noise Type and Wavelet Thresholding the Multitaper Spectrum,” in Advances in Machine Learning and Signal Processing, Lecture Notes in Electrical Engineering series, Switzerland, Springer International Publishing, 2016, pp. 187-200.
  8. Ramanathan SG, Kumar BP, Ananda CM, Jayakumar EP, “Design of graphics processing framework on FPGA,” in IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT-2016), 20-21 May 2016 at Sri Venkateshwara College of Engineering, Bengaluru, India, (pp. 387-391).
  9. Dinesh MV, Ananda CM, Kumar BP, Jayakumar EP, “Design and implementation of fiber channel based high speed receiver protocol for avionics on FPGA,” in IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT-2016), 20-21 May 2016 at Sri Venkateshwara College of Engineering, Bengaluru, India, (pp. 1195-1200).
  10. Narapureddy P, Ananda CM, Kumar BP, Jayakumar EP, “Design and implementation of fiber channel based high speed serial transmitter for data protocol on FPGA,” in IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT-2016), 20-21 May 2016 at Sri Venkateshwara College of Engineering, Bengaluru, India, (pp. 926-931).

1. Digital System Design

2. DSP System Design

3. VLSI System Design

Ongoing

ARATHI SANKAR P (Full Time)

ANUJA GEORGE (Full Time - QIP)

MIDDE VENKATA SIVA (Full Time)

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