Room : 304, EC I Block
Email dhanaraj@nitc.ac.in
Office Phone 04952286710
Mobile 08547616464
Home Address Kakkanattu House, Neendoor, Vadakkekara P.O., N.Paravoor, Ernakulam District, Kerala
Areas Of Interest Low Power Analog IC Design, VLSI Architectures for Signal Processing, Neuromorphic Chip Design

Ph.D.  :IIT Delhi, 2017

M.Tech.: NIT Calicut,Digital Systems & Communication, 2007

B.Tech.: NIT Calicut, Electronics & Communication Engineering,2003

UG THEORY COURSES:

1. Electromagnetic Field Theory (2006,2010,2017, 2018)
2. Communication Switching Systems(2006,2007)
3. Basic Electronics Engineering (2006 Summer Course)
4. Linear Integrated Circuits (2006,2007,2008)
5.  Digital MOS Circuits (2008)/Digital Integrated Circuits (2009)
6. Network Theory (2008,2014,2015)
7. Electronic Circuits-1 (2009,2014,2015)
8. Electronic Circuits II (2013)
9. VLSI Circuits & Systems (2015,2016,2017)
10. Signals and Systems (2016)
11. Basic Electrical Sciences (2017)


PG THEORY COURSES:


1. Digital Integrated Circuits Design (2007)
2. Analog Integrated Circuit Design (2009, 2015)

UG LAB COURSES:

1. Analog Communication Lab (2005)
2. Linear Integrated Circuits Lab (2006,2007,2008)
3. Basic Electronics Engineering Lab (2006)
4. Electronics Lab - CSE(2006)
5. Device Characterization Lab (2009)
6. Electronic Circuits Lab II (2013,2014,2016,2017)
7. Electronic Circuits Lab I (2014,2015)


UG COURSES OFFERED (AS ADHOC LECTURER DURING 2003-04):

1. Analog & Digital Communication Systems (Electrical Dept.)
2. Electromagnetic Field Theory

1. Warden - PG1 Hostel (2007-08)

2. Program Ofiicer - National Service Scheme (2005-08)

3. Secretary - Alumni Association (2005-08)

4. Associate Editor - NITC Research Review (2007-10)

5.Deputy chairperson of UG admission committee (2009-10)

6. ECED purchase coordinator (2016 -2018)

7. Information facilitator/Liaison officer/Department Website incharge (2016 -2018)

8. Branch Counselor - IEEE SB NITC (Feb 2015- Jan 2017)

9.  Faculty Advisor - B.Tech ECE (2006-2010, 2015 onwards)

10. ECED member in institute curriculum revision committee (2013 onwards)

11. First Year B.Tech. Coordinator (July 2018 onwards)

 

1. EC3011 Electronic Circuits II

2. EC6202D Analog Integrated Circuit Design

Research Scholars:

1. Ms. Sona Alex 
Topic of research: Channel Coding and Cryptosystem Implementations to Suit 5G Challenges

(Combined Guidance with Dr. Deepthi P. P.)
2. Mr. Nithin Thomas Abraham 
Topic of Research: Power Management in Low Power Circuits

 

M.Tech Major Projects:
 
 1.  SRAM Design and Standby Power Minimization (2007-08)
 2. Design of Low Power Wideband Analog Multiplier(2008-09)
 3. Design and Simulation of High Gain-Bandwidth Fully Differential Operational Amplifier(2008-09)
 4. EMG Acquisition System for Control Applications(Wheel Chair Control)
( Combined Guidance With Mr. Raghu C.V., Assistant Professor, ECED) (2009-10) 5. Low Power Ternary CAM Design and Simulation (2009-10) 6. A gm/ID based High PSR Low Dropout Regulator Design (2013-14) 7. Hardware Design For Secret Key Cryptosystem Using Regular Quasi-Cyclic LDPC
Codes (2014-15) 8. ASIC Implementation of Real Time Stereo Vision Algorithm Using Discrete Cosine Transform (2014-15) 9. ASIC Implementation of Low Power-High Speed Fixed/Floating point MAC Unit (2015-16)
10. Hardware Implementation of Code based Cryptographic system using QC-LDPC (Combined Guidance with Dr. Deepthi P. P.)(2016-18)
11. Design of Low Power Event Driven Clockless Level Crossing ADC (combined Guidance with Mr. Bhuvan B.)(2016-17)
12. ASIC Implementation of Regular LDPC-CC Encoder and Decoder (2017-18)
13. Tunable Ultra Low Power Voltage Reference (Ongoing)
 
 B.Tech Major Projects: 
1. Implementation Of A Video Conferencing Application Over A Wired Network ( Combined 
Guidance With Dr. P.S. Sathidevi, Asst.Professor,ECED) (2005-06)
2. Desgin and Simulation of a High Slew Rate Operational Amplifier (2007-08)

3. FPGA Implementaion of AES Cryptosystem (2007-08)
4. Selective Image Encryption( Combined Guidance With Ms. Deepthi P.P., Lecturer, ECED) (2008-09)
5. Implementation of Reed Solomon Encoder and Decoder (2008-09)
6. FPGA Implementation of Network Intrution Detection System(2008-09)
7. Wearable Emergency Alert System (2009-10)
8. SONAR Aided Object Localization (Combined Guidance with Dr. Sameer S.M.) (2014-15)

9. BIO Monitoring System using FPGA board (2016-17)
10. Monocular Visual Simultaneous Localization and Mapping (combined guidance with Dr. Sudheer A. P, MED) (2016-17)
11. Low Cost Touch Sensitive Screen Module (2016-17)
12. Implementation of 2D DCT in Digital and Analog Domains (2017-18)
13. FFT Architectures for Motion Estimation Using Phase Correlation (Combimed Guidance with Dr. Sreelekha G.)(2017-18)
14. SAD Based Real Time Stereo Vision Algorithms: A Comparative Study and Protoype Implementation (2017-18)
15. Hardware Implementation of Deep Neural Networks (Ongoing)
16. LDPC Codes: Encoder and Decoder (Ongoing)
 
B.Tech Mini Projects:

1. Digital Multimeter(2006)
2. Thermal And Remote Control of Fan Speed (2007)
3. Speaker Recognition Using Arificial Neural Networks (2007)
4. Barcode Reader And Decoder (2007)
5. Digital Spghymomanometer (2007)
6. Design and Implementation of a Function Generator (2008)
7. GSM Enabled GPS Tracking Device (2008)
8. USB Host Controller (2009)
9. Fire Alarm Using GSM Module (2014)
10.Metal and Explosive Detection (2014)
11.EMG Signal Acquisition and Biofeedback System Implementation(2014)
12. Electrocardiography (ECG) Monitoring (2015)
13.
Dr. X-Box (Physiotherapy In Form Of Game) (2015)
14.  Digital Sampling Android Oscilloscope (2015)
15. Visual Light Communication (2017)
16. Solar Battery Charger Using MPPT (2017)
17. A Blind Assistive Device (2018)
18. Implementation of Memristor and its Application (2018)
  1. Jinesh K.B, and K.J. Dhanaraj, " A Low Power Architectute of Real Time Stereo Vision Algorithm Using Discrete Cosine Transform", TENCON 2017 IEEE Region 10 Conference, Penang, Malaysia, 5-8 Nov, 2017
  2. Celine Mary Stuart, Spandana K., Dhanaraj K.J., Deepthi P. P., "Design and Implementation of Hardware-Efficient Modified Rao-Nam Scheme with High Security for Wireless Sensor Networks", Journal of Information Security and Applications, vol 29, pp 65-79, 2016 (doi:10.1016/j.jisa.2016.03.004)
  3. Dhanaraj K.J and Basabi Bahumik, “ Modulation Ratio of Layer 2/3 cells in Primary Visual Cortex: A Model Based Study”, 2015 International Joint Conference on Neural Networks (IJCNN), Killarney, Ireland, July 12-17, 2015
  4. Aravind E. Vijayan, Asma Beevi K.T., Kevin Jerome, Karthika C. Ravaindran, Dhanaraj K.J., " High SNR EMG Acquisition System for Biofeedback applications",IEEE - International Conference on Computational Intelligence & Communication Technology, Gaziabad, India, Feb. 13-14, 2015
  5. Prakash, Gundabathina, and K. J. Dhanaraj, "gm/Ibased Design of High PSR Low dropout Regulator for SoC Applications", 2015 International Conference on Communication, Information & Computing Technology (ICCICT),, Mumbai, India,  Jan. 16-17, 2015
  6. Jerome, Kevin, Varghese Tony, R. Vinayak, and K. J. Dhanaraj. "Indoor Navigation Using Visible Light Communication." 2014 IEEE Texas Instruments  India Educators' Conference (TIIEC), pp. 46-52,2014.
  7. Dhanaraj. K.J, Deepthi.P.P and P.S. Sathidevi, "FPGA Implementation of a Pseudo Random Bit Sequence Generator Based on Elliptic Curves", ICGST- PDCS Journal, Volume 7, Issue 1, pp. 23-31, May 2007
  8. Nithin V.S., Deepthi P.P., Dhanaraj K.J., Sathidevi P.S., "Stream Ciphers Based on Elliptic Curves", International Conference on Computational Intelligence and Multimedia Applications (ICCIMA 2007), Sivakasi, Tamilnadu, December 13-15, 2007

Official Positions:

1. Treasurer, IEEE Malabar Sub Section

2. Secretary, Circuits and Systems Society, IEEE Kerala chapter

Membership:

1. Member - IEEE

2. Member - IEEE Solid-State Circuits Society

3. Member - IEEE Circuits and Systems Society

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