Room IT-Lab : 202
Email chandan@nitc.ac.in
Office Phone -
Mobile +91 9198793266
Areas Of Interest 1) Compact Modeling and Numerical simulation analysis of Semiconductor devices; 2) Electrical Characterization of semiconductor devices in sub-THz and THz frequency range; 3) Electronics for Quantum Computing Application; 4) Application of Machine Learning in Semiconductor device research.

1) Compact Modeling and Numerical Simulation: Conventional Si and alternative channel material FETs, High power device GaN HEMT, LDMOS, etc.;

2) Electrical Characterization of semiconductor devices in sub-THz and THz: On-wafer test structure design, Calibration methods, De-embedding Techniques, EM simulation analysis, EM-SPICE co-simulation analysis, etc.;

3) Electronics for Quantum Computing application and Machine Learning application in the Semiconductor Device research.

 

 

 

 

Journal:

  1. C. Yadav, M. Deng, S. Fregonese, M. Cabbia, M. D. Matos, B. Plano, and T. Zimmer, “Importance and Requirement of frequency band specific RF probes EM Models in sub-THz and THz Measurements up to 500 GHz” accepted for publication in IEEE Transactions on Terahertz Science and Technology, 2020.
  2. S. Fregonese, M. Deng, M. D. Matos, C. Yadav, S. Joly, B. Plano, C. Raya, B. Ardouin and T. Zimmer, “Comparison of On-wafer TRL calibration to ISS SOLT calibration with Open-Short De-embedding up to 500 GHz", in IEEE Transactions on Terahertz Science and Technology, vol. 9, no. 1, pp. 89 - 97, Jan. 2019.
  3. C. Yadav, P. Rastogi, T. Zimmer and Y. S. Chauhan, "Charge-Based Modeling of Transition Metal Dichalcogenide Transistors Including Ambipolar, Trapping, and Negative Capacitance Effects," in IEEE Transactions on Electron Devices, vol. 65, no. 10, pp. 4202-4208, Oct. 2018.
  4. M. D. Ganeriwala, C. Yadav, F. G. Ruiz, E. G. Marin, Y. S. Chauhan and N. R. Mohapatra, "Modeling of Quantum Confinement and Capacitance in III–V Gate-All-Around 1-D Transistors," in IEEE Transactions on Electron Devices, vol. 64, no. 12, pp. 4889-4896, Dec. 2017.
  5. P. Jain, P. Rastogi, C. Yadav, A. Agarwal, and Y. S. Chauhan, “Band-to-Band Tunneling in Г valley for Ge Source Lateral Tunnel Field Effect Transistor: Thickness scaling", Journal of Applied Physics, vol. 122, pp. 014502, 2017.
  6. C. Yadav, M. D. Ganeriwala, N. R. Mohapatra, A. Agarwal and Y. S. Chauhan, "Compact Modeling of Gate Capacitance in III–V Channel Quadruple-Gate FETs," in IEEE Transactions on Nanotechnology, vol. 16, no. 4, pp. 703-710, July 2017.
  7. P. Jain, C. Yadav, A. Agarwal, Y. S, Chauhan, “Surface Potential based Modeling of Charge, Current, and Capacitances in DGTFET including Mobile Channel Charge and Ambipolar Behavior” in Solid-State Electronics, vol. 134, pp. 74-81, 2017.
  8. C. Yadav, M. Agrawal, A. Agarwal and Y. S. Chauhan, "Compact Modeling of Charge, Capacitance, and Drain Current in III–V Channel Double Gate FETs," in IEEE Transactions on Nanotechnology, vol. 16, no. 2, pp. 347-354, March 2017.
  9. C. Yadav, A. Agarwal and Y. S. Chauhan, "Compact Modeling of Transition Metal Dichalcogenide based Thin body Transistors and Circuit Validation," in IEEE Transactions on Electron Devices, vol. 64, no. 3, pp. 1261-1268, March 2017.
  10. M. D. Ganeriwala, C. Yadav, N. R. Mohapatra, S. Khandelwal, C. Hu and Y. S. Chauhan, "Modeling of Charge and Quantum Capacitance in Low Effective Mass III-V FinFETs," in IEEE Journal of the Electron Devices Society, vol. 4, no. 6, pp. 396-401, Nov. 2016.
  11. C. Yadav, J. P. Duarte, S. Khandelwal, A. Agarwal, C. Hu and Y. S. Chauhan, "Capacitance Modeling in III–V FinFETs," in IEEE Transactions on Electron Devices, vol. 62, no. 11, pp. 3892-3897, Nov. 2015.
  12. H. Agarwal, C. Gupta, P. Kushwaha, C. Yadav, J. P. Duarte, S. Khandelwal, C. Hu, and Y. S. Chauhan, "Analytical Modeling and Experimental Validation of Threshold Voltage in BSIM6 MOSFET Model," in IEEE Journal of the Electron Devices Society, vol. 3, no. 3, pp. 240-243, May 2015.
  13. P. Kushwaha, N. Paydavosi, S. Khandelwal, C. Yadav, H. Agarwal, J. P. Duarte, C. Hu, and Y. S. Chauhan, “Modeling the impact of substrate depletion in FDSOI MOSFETs,” in Solid-State Electronics, vol. 104, pp. 6-11, 2015.
  14. C. Yadav, P. Kushwaha, S. Khandelwal, J. P. Duarte, Y. S. Chauhan and C. Hu, "Modeling of GaN-Based Normally-Off FinFET," in IEEE Electron Device Letters, vol. 35, no. 6, pp. 612-614, June 2014.
  15. S. Khandelwal, C. Yadav, S. Agnihotri, Y. S. Chauhan, A. Curutchet, T. Zimmer, J. C. Dejaeger, N. Defrance and T. A. Fjeldly, "Robust Surface-Potential-Based Compact Model for GaN HEMT IC Design," in IEEE Transactions on Electron Devices, vol. 60, no. 10, pp. 3216-3222, Oct. 2013.

Conference Proceedings:

  1. K. Nandan, C. Yadav, P. Rastogi, A. T.-Lopez, A. M.-Sanchez, E. G. Marin, F. G. Ruiz, S. Bhowmick, Y. S. Chauhan, "Compact Modeling of Surface Potential and Drain Current in Multi-layered MoS2 FETs," 4th IEEE Electron Devices Technology & Manufacturing Conference (EDTM), Penang, Malaysia, 2020, pp. 1-4.
  2. C. Yadav, S. Fregonese, M. Deng, M. Cabbia, M. D. Matos, and T. Zimmer, “On the Variation in Short-Open De-embedded S-parameter Measurement of SiGe HBT up to 500 GHz", in 12th German Microwave Conference (GeMiC), Stuttgart, Germany, March 2019, pp. 264 - 267.
  3. C. Yadav, S. Fregonese, M. Deng, M. Cabbia, M. D. Matos, M. Jaoul and T. Zimmer, “Analysis of Test Structure design Induced Variation in on Si On-wafer TRL calibration in sub-THz", in 32nd IEEE Int. Conference on Microelectronics test Structures, Fukuoka, Japan, March 2019, pp. 132 - 136.
  4. Y. S. Chauhan, C. Yadav, A. Dasgupta and P. Rastogi, "Atomistic Simulation and Compact Modeling of Atomically Thin Transistors," 2018 10th International Conference on Electrical and Computer Engineering (ICECE), Dhaka, Bangladesh, 2018, pp. 1-6.
  5. C. Yadav, M. Deng, S. Fregonese, M. De Matos, B. Plano and T. Zimmer, "Impact of on-Silicon De-Embedding Test Structures and RF Probes Design in the Sub-THz Range," 48th European Microwave Conference (EuMC), Madrid, Spain, Sept. 2018, pp. 21-24.
  6. C. Yadav, M. Deng, M. D. Matos, S. Fregonese, and T. Zimmer, “Importance of Complete Characterization Setup on On-wafer TRL calibration in sub-THz Range” 31st IEEE International Conference on Microelectronic Test Structures (ICMTS), Austin, TX, March 2018, pp. 197-201.
  7. C. Yadav, A. Dutta, S. Sirohi, T. Ethirajan and Y. S. Chauhan , “Unified Model for Sub-Bandgap and Conventional Impact Ionization in RF SOI MOSFETs with Improved Simulator Convergence” 29th International Conference on VLSI Design and 2016 15th International Conference on Embedded Systems (VLSID), Kolkata, Jan. 2016, pp. 328-333.
  8. C. Yadav, A. Agarwal and Y. S. Chauhan, “Analysis of Quantum Capacitance Effect in Ultra-Thin-Body III-V Transistor” 29th International Conference on VLSI Design and 2016 15th International Conference on Embedded Systems (VLSID), Kolkata, Jan. 2016, pp. 571-572.
  9. C. Yadav, P. Kushwaha, H. Agarwal and Y. S. Chauhan,“Threshold voltage modeling of GaN based normally-off tri-gate transistor” 11th IEEE India Conference (INDICON), Pune, Dec. 2014, pp. 1-4.
  10. P. Kushwaha, C. Yadav, H. Agarwal, J. Srivatsava, S. Khandelwal, J. P. Duarte, C. Hu and Y. S. Chauhan , “BSIM-IMG with improved surface potential calculation recipe” Annual IEEE India Conference (INDICON), Pune, 2014, pp. 1-4.
  11. A. Dasgupta, C. Yadav, P. Rastogi, A. Agarwal and Y. S. Chauhan, “Analysis and modeling of quantum capacitance in III-V transistors” IEEE 2nd International Conference on Emerging Electronics (ICEE), Bangalore, Dec. 2014, pp. 1-4.
  12. J. R. Sahoo, H. Agarwal, C. Yadav, P. Kushwah, S. Khandewal, R. Gillon, Y. S. Chauhan, “High voltage LDMOSFET modeling using BSIM6 as intrinsic-MOS model” IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia), Visakhapatnam, Dec. 2013, pp. 56-61.
  13. H. Agarwal, S. Venugopalan, M. Chalkiadaki, N. Paydavosi, J. P. Duarte, S. Agnihotri, C. Yadav, P.Kushwaha, Y. S. Chauhan, C. C. Enz, A. Niknejad and C. Hu , “Recent enhancements in BSIM6 bulk MOSFET model” International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), Glasgow, Sept. 2013, pp. 53-56.
  14. Y. S. Chauhan, S. Venugopalan, N. Paydavosi, P. Kushwaha, S. Jandhyala, J. P. Duarte, S. Agnihotri C. Yadav, H. Agarwal, A. Niknejad and C. Hu, “BSIM compact MOSFET models for SPICE simulation” Proceedings of the 20th International Conference Mixed Design of Integrated Circuits and Systems - MIXDES 2013, Gdynia, Poland, June 2013, pp. 23-28. 

 

Other Publications in Workshops/Conferences:

  1. S. Fregonese, M. Deng, M. Cabbia, C. Yadav, S. R. Panda, T. Zimmer “On wafer small signal characterization beyond 100 GHz for compact model assessment49th European Microwave Conference (EuMC), Paris, France, Sept. 2019.
  2. M. Cabbia, M. Deng, C. Yadav, S. Fregonese, M. D. Matos, T. ZimmerCaractérisation RF de transistors bipolaires à hétérojonction SiGe jusqu’à 500 GHz13ème Colloque National du GDR SOC2, Montpellier, France, 19, 20 et 21 juin 2019.
  3. C. Yadav, M. Deng, S. Fregonese, M. D. Matos, and T. Zimmer “Measurement issues of on-Silicon de-embedding test structures in the Sub-THz range30th BipAk, Frickenhausen, Germany, Nov. 2018.
  4. C. Yadav and Y. S. Chauhan, “Modeling of Transition Metal Dichalcogenide Transistors for SPICE SimulationMOS-AK Workshop, Berkeley, USA, Dec. 2016.
  5. C. Yadav, A. Agarwal, and Y. S. Chauhan “Compact Modeling of charge Density and Capacitance in III-V channel Double gate FETs” Int. Workshop on Physics of Semiconductor Devices (IWPSD), Bangalore, India, Dec. 2015.
  6. C. Yadav, A. Agarwal, and Y. S. Chauhan “Effect of Back Bais on Quantum Capacitance in III-V Transistors” SRC TECHCON, Austin, USA, Sep. 2015
  7. C. Yadav, S Khandelwal and Y. S. Chauhan “Modeling of AlGaN/GaN FinFET” Workshop on Compact Modeling, Washington D.C., USA, June 2014.
  8. Y. S. Chauhan, P. Kushwaha, S. Khandelwal, C. Yadav, N. Paydavosi, J. P. Duarte and C. Hu  “BSIM-IMG: Compact Model for UTBBSOI MOSFETs” Workshop on Compact Modeling, Washington D.C., USA, June 2014.

 

 

 

1) B.E. (Electronics & Communication Engineering) from RGPV Bhopal: 2005 - 2009

2) M.Tech. (Microelectronics) from IIIT Allahabad: 2009 - 2011

3) Ph.D. (Electrical Engineering) from IIT Kanpur: 2011 - 2017

1) IBM India Pvt. Ltd. (SRDC), Bangalore - June 2014 to Dec. 2014

2) University of Bordeaux, France - July 2017 to June 2019

 

Memberships: Member IEEE; Member IEEE Electron Devices Society

Reviewer:

1. Journal: IEEE Transactions on Electron Devices, IEEE Electron Device Letters, IEEE Transactions on Terahertz Science and Technology, IEEE Sensors Journal, Solid-State Electronics, Microelectronics Journal, Applied Physics Letters, Microelectronics Engineering, IETE Technical Review, Springer - Journal of Computational Electronics.

2. Conference: UPCON-2015, TENCON-2016.

If you are interested in working with me, please send your C.V. to me at chandan@nitc.ac.in. I am looking for motivated and interested B.Tech., M.Tech., Ph.D., and PostDoc candidates.  

Scholarships for Ph.D./postDoc Candidates:

PostDoc Candidate: National Post Doctoral Fellowship (N-PDF), webpage link: https://serbonline.in/SERB/npdf

Ph.D. Candidate: 1.  JRF-NET exam, webpage: https://www.csirhrdg.res.in/Home/Index/1/Default/1246/60 

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