Room ECED-2 : 303
Office Phone 0495-2286723
Home Address Eruppathodiyil House, Opp. RECGVHSS, NITC Campus P.O, NIT Calicut - 673601
Areas Of Interest FPGA/ASIC implementation of signal processing architectures, Digital VLSI Circuits/Systems, Digital Signal Processing
  • PhD: National Institute of Technology, Calicut (2009 - 2014)
    • Thesis Title: Design of Multiplier-less Uniform and Non-uniform Filter Banks Using Meta-heuristic Algorithms
    • Thesis Supervisor: Dr. Elizabeth Elias, Professor, Department of Electronics & Communication Engineering, National Institute of Technology, Calicut
  • M.Tech: VLSI Design, Amrita School of Engineering, Coimbatore (2004 - 2006)
  • B.Tech: Electronics & Communication Engineering, Govt. Model Engineering College, Thrikkakara, Cochin, (2000 - 2004)

Journals: 11

  1. Sudharman S, Bindiya T. S., Design of Power Efficient Variable Bandwidth Non-maximally Decimated FRM Filters for Wideband Channelizer. IEEE Transactions on Circuits and Systems II: Express Briefs. 2019,  66(9), pp. 1597 - 1601
  2. Sudhi Sudharman, Athul D. Rajan, T. S. Bindiya, "Design of a Power-Efficient Low-Complexity Reconfigurable Non-maximally Decimated Filter Bank for High-Resolution Wideband Channels", Circuits, Systems, and Signal Processing (Springer), 2019, 38(6), pp. 2703-2735.
  3. Amir, A., Bindiya, T. S. and Elizabeth Elias, Low-complexity implementation of efficient reconfigurable structure for cost-effective hearing aids using fractional interpolation. Computers & Electrical Engineering, 2019, 74, pp.391-412.
  4. A Amir, J Pragadeeshwaran, T. S. Bindiya, Elizabeth Elias, "Reconfigurable filter bank structures for low complexity digital channelizer using fractional interpolation and MFIR filters with cosine modulation", AEU-International Journal of Electronics and Communications (Elsevier), 2018, 94, pp. 262-276
  5. Amir A., Bindiya T. S. and Elizabeth Elias, “Design and Implementation of Reconfigurable Filter Bank Structure for Low Complexity Hearing Aids using 2-level Sound Wave Decomposition”, Biomedical Signal Processing and Control (Elsevier), 2018, 43, pp. 96-109
  6. Bindiya, T. S. and Elizabeth Elias, "Meta-heuristic evolutionary algorithms for the design of optimal multiplier-less recombination filter banks.", Information Sciences (Elsevier), 2016, 339, pp. 31-52, doi:10.1016/j.ins.2015.12.018.
  7. Bindiya, T. S. and Elizabeth Elias, "Design of FRM-based MDFT filter banks in the canonic signed digit space using modified meta-heuristic algorithms.", International Journal of Signal and Imaging Systems Engineering (Inderscience), 2016, 9(1), pp.20-37.
  8. Bindiya T. S. and Elizabeth Elias, “Design of Totally Multiplier-less Sharp Transition Width Tree Structured Filter Banks for Non-uniform Discrete Multitone System", International Journal of Electronics and Communications (Elsevier), 2015 Mar 31; 69(3): 655-65.
  9. Bindiya T. S. and Elizabeth Elias, “Modified meta-heuristic Algorithms for the Optimal Design of Multiplier-Less Non-uniform Channel Filters”, Circuits, Systems, and Signal Processing (Springer), March 2014, Volume 33, Issue 3, pp. 815-837.
  10. Bindiya T. S. and Elizabeth Elias, “Meta-heuristic Algorithms for the Design of Multiplier-less Non-Uniform Filter Banks based on Frequency Response Masking”, Soft Computing (Springer), July 2014, Volume18, Issue 8, pp. 1529-1547.
  11. Bindiya T. S. and Elizabeth Elias, “Design of Multiplier-less Sharp Transition Width Non-Uniform Filter Banks Using Gravitational Search Algorithm”, International Journal of Electronics (Taylor and Francis), 2015 Jan 2;102(1):48-70.

Conferences: 5

  1. Sreelekha K. R., Bindiya T. S., "A New Multiplier-free Transformation for the Design of Hardware Efficient Circularly Symmetric Wideband 2D Filters", IEEE TENCON 2019, 17 - 20 October 2019 at Hotel Grand Hyatt, Bolgatty, Kochi, Kerala, India.
  2. Sudhi Sudharman, Bindiya T. S., "Design and Implementation of Maximally Decimated Polyphase Filter Bank for Power and Delay Efficient Digital Hearing Aids", IEEE TENCON 2019, 17 - 20 October 2019 at Hotel Grand Hyatt, Bolgatty, Kochi, Kerala, India.
  3. Sudhi Sudharman, Bindiya T. S., "Reconfigurable Non-Maximally Decimated Filter Bank Based Wideband Channelizer for VLBI", Canadian Conference on Electrical and Computer Engineering, 30 April - 3 May 2017, Windsor, Canada.
  4. Amir A, Rakesh Inani, Bindiya T. S., Elizabeth Elias, “Reconfigurable Low Complexity Hearing Aid System using Adjustable Filter Bank”, IEEE TENCON 2016, 22 - 25 November 2016, Marina Bay Sands, Singapore.
  5. Kaka Radhakrishna, Nisha Haridas, Bindiya T. S., Elizabeth Elias, “Cuckoo Optimization Algorithm for the Design of a Multiplier-less Sharp Transition Width Modified DFT Filter Bank”, International Conference On Advanced Engineering Optimization Through Intelligent Techniques, S.V. National Institute of Technology, Gujarat, India, July 2013.

UG Courses

  1. Digital Integrated Circuits 
  2. Modeling and Testing of Digital Systems
  3. Logic Design 
  4. Computer Organization and Architecture
  5. Network Theory  
  6. Signals and Systems
  7. Basic Electronics

PG Courses

  1. VLSI System Design 
  2. Digital Integrated Circuit Design
  3. Digital System Design
  4. Low Power VLSI
  5. Testing and Verification of VLSI Circuits 
  6. DSP System Design
  7. Multirate Signal Processing


Completed - 1

  1. Amir A, Design and Implementation of Fractional Interpolation Based Reconfigurable and Hardware Efficient Digital Filter Structures (Coguided with Dr. Elizabeth Elias)

Thesis Submitted - 1

  1. Sudhi Sudharman, Design and Synthesis of Reconfigurable-non-maximally Decimated and Maximally Decimated Polyphase Filter Bank Based Structures

Ongoing - 2

  1. Hareesh (Multirate Filter Banks)
  2. Sreelekha K. R. (Multirate Filter Banks)
  3. Treasa Joseph (Digital VLSI Circuits)


M. Tech Major Projects

Ongoing - 9

Completed - 25

  1. Manuprasad V. (Implementation of Power and Area Efficient Reconfigurable FIR Filters Using Inexact Adders and Subtractors) (2018 - 2019)
  2. Balaraj M. (Fault Injection Framework Deployment to Enable Concurrent Fault Simulations and Diagnostic Coverage Validation, Coguided with Mr. Siva Prasad Kota, Technical Lead, Intel Technology India Pvt. Ltd.) (2018 - 2019)
  3. Shivaramakrishna (2018 - 2019)
  4. Niyas K. (Performance Analysis of SoC Interconnect Bus Using System C, Coguided with Mr. Raja Jondhle, Project Program Manager, Intel Technology India Private Limited, Bangalore) (2018 - 2019)
  5. Ananya Suresh (Power Optimization in High Frequency CPU Core Through Multiple Voltage Domain, Coguided with Mr. Tiju Jacob and Mr. Satish Sethuraman, Intel Technology India Private Limited, Bangalore) (2018 - 2019)
  6. Reshma Abraham (Design of Scalable and Configurable IP And IP Collaterals, Coguided with Mr. Sunil Aggarwal, Sr. Logic Design Engineer, Intel Technology India Private Limited, Bangalore) (2018 - 2019)
  7. Athul D Rajan (Non-maximally Decimated Filter Banks for Wideband Applications) (2017 - 2018)
  8. T. Sandeep (A High PerformanceFIR Filter with Low Complexity) (2017 - 2018)
  9. Rupesh Kumar Yadav (Design and Implementation of RISC Based Controller for Inertial Sensors) (2017 - 2018)
  10. Vinod Kumar B. (A Constant Multiplier Architecture based on Vertical-Horizontal Binary Common Sub-Expression Elimination Algorithm for Re-Configurable FIR Filter Synthesis) (2017 - 2018)
  11. Reshma M. (Power Optimization in High Speed Circuit Design, Co-guided with Shanthi Rangaswamy, Design Engineer, Intel Tech. India Pvt. Ltd.) (2017 - 2018)
  12. Sino V Antony (Datapath Design of Functional Unit Blocks in Sub-14nm Microprocessor Core, Co-guided with Mr. Karthik Ramanathan, Design Manager, Intel Corporation) (2016 - 2017)
  13. Adwaid Suresh (Xtensa Processor Verification, Co-guided with Nitika Chandrakar, Lead Design Engineer, Cadence Pune) (2016 - 2017)
  14. Narasimhamurthy T R (Generation and Study Of Library Exchange Format in SoC Flow, Komila Sabharwal, ST Microelectronics) (2016 - 2017)
  15. Shabanm Toppo (FPGA implementation of Non-maximally decimated filter banks) (2016 - 2017)
  16. Vishnu Prasad K V (Verification challenges and solutions in complex out-of-order advanced microprocessors, Co-guided with Nagesh Vishnumurthy, Sr.Manager, IC Design, Broadcom Corporation) (2015 - 2016)
  17. Anoop Martin (Backend implementation for low geometry nodes, Co-guided with Satyakam Sudershan, Design Engineering, Cadence AMS Design) (2015 - 2016)
  18. Jissmon Joseph (Low Dropout Regulator, Co-guided with Satheesh Kumar, Manager, Layout/Mask Design, Broadcom Corporation) (2015 - 2016)
  19. Rajesh Ranjan (DFT insertion for 16nm IPs at high speed, Co-guided with Dheeraj Jasti, Engineer, Principal - IC Design, Broadcom Corporation) (2015 - 2016)
  20. Duddela Amareswari (Ultrasonic Waist Belt for Visually Challenged) (2015 - 2016)
  21. Muneer K. (Design checks in front-end environment for smart and fast hand-off, Co-guided with Mr. AtulNauriyal, STMicroelectronics) (2014 - 2015)
  22. Jinju P. K. (Physical Design of an SRAM module in 28nm technology, Co-guided with Mr. Kamal Kumar, Sr. Manager, Broadcom Research India Pvt Ltd) (2014 - 2015)
  23. B Murali Krishna (Design and characterization of general purpose I/O buffer in 28nm CMOS technology, Co-guided with Mr. Mohammad IrshadRizvi, project leader, STMicroelectronics) (2013 - 2014)
  24. M.C.Arun (FPGA based USB device core) (2009 - 2010)
  25. Gudla Sarvajee (FPGA implementation of OFDM modulation, Co-guided with Mr. SandipPandey, Project Manager, Intel Corporation)(2009 – 2010)

B. Tech Major Projects

Ongoing - 3

Completed - 7

  1. Multiple Object Tracking (2017 - 2018)
  2. Wimax Implementation (20156 - 2017)
  3. Image based surveillance using face detection (2015 - 2016)
  4. Wireless voice communication (2015 - 2016)
  5. FPGA implementation of Stream Cipher Cryptographic Techniques and Performance Evaluation (2014 - 2015)
  6. FPGA implementation of high speed FIR filter based on Vedic Mathematics (2014 - 2015)
  7. Implementation of the encryption technique Pretty Good Privacy (PGP) in mobile phones (2012 - 2013)
  • ECED Time Table in charge (2015 Onwards)
  • ECED Purchase Coordinator (2018 Onwards)
  • Faculty in charge of Dept. Staff amenities/Seminar Halls/Projectors (2015 - 2016)
  • Member of ECED Time Table Committee (2013 - 2015) 
  • Faculty advisor of 2017-2021 ECE B. Tech Batch
  • Member, B Tech major project evaluation committee (2015 - 2018)
  • Member, B Tech mini project evaluation committee (2012 - 2015)
  • Faculty advisor of 2009-2013 ECE B. Tech Batch
  • Ladies Hostel Warden (2009 - 2010)

Assistant Professor, ECED at NIT Calicut from January 2009 onwards

ASIC Verification Engineer, Flowgic India Pvt Ltd, Chennai from January 2007 to January 2009