Room ECED-2 : 303
Email bindiyajayakumar@nitc.ac.in
Office Phone 0495-2286723
Home Address Eruppathodiyil House, Opp. RECGVHSS, NITC Campus P.O, NIT Calicut - 673601
Areas Of Interest Digital Signal Processing, Multirate Filter Banks, VLSI implementation of signal processing architectures
  • PhD: National Institute of Technology, Calicut (2009 - 2014)
    • Thesis Title: Design of Multiplier-less Uniform and Non-uniform Filter Banks Using Meta-heuristic Algorithms
    • Thesis Supervisor: Dr. Elizabeth Elias, Professor, Department of Electronics & Communication Engineering, National Institute of Technology, Calicut
  • M.Tech: VLSI Design, Amrita School of Engineering, Coimbatore (2004 - 2006)
  • B.Tech: Electronics & Communication Engineering, Govt. Model Engineering College, Thrikkakara, Cochin, (2000 - 2004)

Journals

  1. Bindiya, T.S. and Elias, E., "Meta-heuristic evolutionary algorithms for the design of optimal multiplier-less recombination filter banks.", Information Sciences (Elsevier), 2016, 339, pp.31-52, doi:10.1016/j.ins.2015.12.018.
  2. Bindiya, T.S. and Elias, E., "Design of FRM-based MDFT filter banks in the canonic signed digit space using modified meta-heuristic algorithms.", International Journal of Signal and Imaging Systems Engineering (Inderscience), 2016, 9(1), pp.20-37.
  3. Bindiya T. S., Elizabeth Elias, “Design of Totally Multiplier-less Sharp Transition Width Tree Structured Filter Banks for Non-uniform Discrete Multitone System", International Journal of Electronics and Communications (Elsevier), 2015 Mar 31; 69(3): 655-65, http://dx.doi.org/10.1016/j.aeue.2014.12.004
  4. Bindiya T. S., Elizabeth Elias, “Modified meta-heuristic Algorithms for the Optimal Design of Multiplier-Less Non-uniform Channel Filters”, Circuits, Systems, and Signal Processing (Springer), March 2014, Volume 33, Issue 3, pp. 815-837, http://dx.doi.org/10.1007/s00034-013-9662-8.
  5. Bindiya T. S., Elizabeth Elias, “Meta-heuristic Algorithms for the Design of Multiplier-less Non-Uniform Filter Banks based on Frequency Response Masking”, Soft Computing (Springer), July 2014, Volume18, Issue 8, pp. 1529-1547, http://dx.doi.org/10.1007/s00500-013-1158-8.
  6. Bindiya T. S., Elizabeth Elias, “Design of Multiplier-less Sharp Transition Width Non-Uniform Filter Banks Using Gravitational Search Algorithm”, International Journal of Electronics (Taylor and Francis), 2015 Jan 2;102(1):48-70, http://dx.doi.org/10.1080/00207217.2014.905992.
  7. BindiyaT.S., Elizabeth Elias, “Design of multiplier-less sharp transition width MDFT filter banks using modified meta-heuristic algorithms”, International Journal of Computer Applications, Published by Foundation of Computer Science, New York, USA, 88(2):1-14, February 2014.
  8. Bindiya. T. S, V. Sathishkumar, Elizabeth Elias, “Design of Low power and Low Complexity Multiplier-less Reconfigurable Non-uniform Channel filter using Genetic Algorithm”, Global Journal of Researches in Engineering - F (Electrical and Electronics Engineering), Vol. 12, Issue. 6, May, 2012, pp. 7-19.
  9. Bindiya T. S., Elizabeth Elias, “Design of Multiplier-less Reconfigurable Non- uniform Channel Filters using Meta-heuristic Algorithms”, International Journal of Computer Applications, Published by Foundation of Computer Science, New York, USA, 59(11):1-11, December 2012.

Conferences

  1. Sudhi Sudharman, Bindiya T. S., "Reconfigurable Non-Maximally Decimated Filter Bank Based Wideband Channelizer for VLBI", Canadian Conference on Electrical and Computer Engineering , 30 April - 3 May 2017, Windsor, Canada.
  2. Amir A, Rakesh Inani, Bindiya T. S., Elizabeth Elias, “Reconfigurable Low Complexity Hearing Aid System using Adjustable Filter Bank”, IEEE TENCON 2016, 22 - 25 November 2016, Marina Bay Sands, Singapore.
  3. Kaka Radhakrishna, Nisha Haridas, Bindiya T. S., Elizabeth Elias, “Cuckoo Optimization Algorithm for the Design of a Multiplier-less Sharp Transition Width Modified DFT Filter Bank”, International Conference On Advanced Engineering Optimization Through Intelligent Techniques, S.V. National Institute of Technology, Gujarat, India, July 2013.

UG Courses

  1. Basic Electronics 
  2. Logic Design  
  3. Network Theory  
  4. Signals and Systems 
  5. Modeling and Testing of Digital Systems 
  6. Digital Integrated Circuits 

PG Courses

  1. VLSI System Design 
  2. Basics of VLSI
  3. Low Power VLSI
  4. Testing and Verification of VLSI Circuits 
  5. DSP System Design
  6. Multirate Signal Processing

PhD

Ongoing - 3

  1. Amir A (Multirate Filter Banks)
  2. Sudhi Sudharman (Non-Maximally Deceimated Filter Banks)
  3. Hareesh (Multirate Filter Banks)

M. Tech Major Projects

Ongoing - 4

  1. Sino V Antony (Datapath Design of Functional Unit Blocks in Sub-14nm Microprocessor Core, Co-guiding with Mr. Karthik Ramanathan, Design Manager, Intel Corporation)
  2. Adwaid Suresh (Xtensa Processor Verification, Co-guiding with Nitika Chandrakar, Lead Design Engineer, Cadence Pune)
  3. Narasimhamurthy T R (Generation and Study Of Library Exchange Format in SoC Flow, Komila Sabharwal, ST Microelectronics)
  4. Shabanm Toppo (FPGA implementation of Non-maximally decimated filter banks)

Completed - 10

  1. Vishnu Prasad K V (Verification challenges and solutions in complex out-of-order advanced microprocessors, Co-guided with Nagesh Vishnumurthy, Sr.Manager, IC Design, Broadcom Corporation) (2015 - 2016)
  2. Anoop Martin (Backend implementation for low geometry nodes, Co-guided with Satyakam Sudershan, Design Engineering, Cadence AMS Design) (2015 - 2016)
  3. Jissmon Joseph (Low Dropout Regulator, Co-guided with Satheesh Kumar, Manager, Layout/Mask Design, Broadcom Corporation) (2015 - 2016)
  4. Rajesh Ranjan (DFT insertion for 16nm IPs at high speed, Co-guided with Dheeraj Jasti, Engineer, Principal - IC Design, Broadcom Corporation) (2015 - 2016)
  5. Duddela Amareswari (Ultrasonic Waist Belt for Visually Challenged) (2015 - 2016)
  6. Muneer K. (Design checks in front-end environment for smart and fast hand-off, Co-guided with Mr. AtulNauriyal, STMicroelectronics) (2014 - 2015)
  7. Jinju P. K. (Physical Design of an SRAM module in 28nm technology, Co-guided with Mr. Kamal Kumar, Sr. Manager, Broadcom Research India Pvt Ltd) (2014 - 2015)
  8. B Murali Krishna (Design and characterization of general purpose I/O buffer in 28nm CMOS technology, Co-guided with Mr. Mohammad IrshadRizvi, project leader, STMicroelectronics) (2013 - 2014)
  9. M.C.Arun (FPGA based USB device core) (2009 - 2010)
  10. Gudla Sarvajee (FPGA implementation of OFDM modulation, Co-guided with Mr. SandipPandey, Project Manager, Intel Corporation)(2009 – 2010)

B. Tech Major Projects

Ongoing - 1

  1. Wimax Implementation

Completed - 5

  1. Image based surveillance using face detection (2015 - 2016)
  2. Wireless voice communication (2015 - 2016)
  3. FPGA implementation of Stream Cipher Cryptographic Techniques and Performance Evaluation (2014 - 2015)
  4. FPGA implementation of high speed FIR filter based on Vedic Mathematics (2014 - 2015)
  5. Implementation of the encryption technique Pretty Good Privacy (PGP) in mobile phones (2012 - 2013)
  • ECED Time Table in charge (2015 Onwards)
  • Faculty in charge of Dept. Staff amenities/Seminar Halls/Projectors (2015 - 2016)
  • Member of ECED Time Table Committee (2013 - 2015) 
  • Faculty advisor of 2013-2017 ECE B. Tech Batch
  • Member, B Tech major project evaluation committee (2015 Onwards)
  • Member, B Tech mini project evaluation committee (2012 - 2015)
  • Faculty advisor of 2009-2013 ECE B. Tech Batch
  • Ladies Hostel Warden (2009 - 2010)

Assistant Professor, ECED at NIT Calicut from October 2009 onwards

Lecturer, ECED at NIT Calicut from January 2009 to October 2009

 

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